Integrated circuit designs, such as those for modern system-on-a-chip (“SOC”) devices, continue to grow is size and complexity. Shrinking transistor sizes mean that more and more transistors can be included in a circuit design once fabricated as an integrated circuit chip (“chip”), while a greater number of features or components can be packed on the chip. The chip may be any type of fabricated integrated circuit, whether on a single substrate or multiple interconnected substrates. Functional verification of such devices is usually included as part of the circuit design flow to help ensure that the fabricated device functions as intended.
The increasing size and complexity of the circuit designs to be verified (devices under test, “DUT,” also known as designs under verification, “DUV”) mean that the functional verification portion of the design cycle is increasing in length. The verification stage may in some case be the longest stage of the design cycle. For example, running a simulation on a host computer to verify a SOC, or even a sub-portion of the SOC, written in the register transfer language (“RTL”) design abstraction may take anywhere from hours to days. Certain hardware functional verification systems may leverage high-performance hardware to increase the speed of the verification stage, including a plurality of interconnected processor chips. Such systems are also referred to as “hardware emulators” herein.
Hardware emulators are programmable devices used in the verification of hardware designs. A common method of hardware design verification uses processor-based hardware emulators to emulate the DUT. These processor-based emulators sequentially evaluate combinatorial logic levels, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels is known as a cycle; the evaluation of each individual logic level is known as an emulation step.
A hardware emulator generally utilizes a computer workstation for providing emulation support facilities, i.e., emulation software, a compiler, and a graphical user interface to allow a person to program the emulator, and an emulation engine for performing the emulation. The emulation engine is comprised of at least one emulation board, and each emulation board contains individual emulation circuits. Each individual emulation circuit for a processor-based emulator contains multiple emulation processors, and each emulation processor is capable of mimicking a logic gate in each emulation step.
Emulation processor can be connected to data arrays, which are a special memory that has multiple read ports and supplies input data to the emulation processors. The emulation processors evaluate the data in accordance with an instruction word supplied from an instruction memory. One current design limitation of hardware emulators is that the input data provided on the read ports of the data array are not always used by the processor during an emulation step. A related limitation of hardware emulators is that there are other times when the processor has additional availability for a data input during an emulation step, but there are too few data array output ports to provide data to the available processor. Both limitations unnecessarily use up processor bandwidth during an emulation cycle. Furthermore, it is well known that processor bandwidth is a significant limiting factor of hardware emulator performance.